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3-axis, 1 g /2 g /4 g /8 g digital accelerometer data sheet adxl350 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2012 analog devices, inc. all rights reserved. technical support www.analog.com features excellent zero- g bias accuracy and stability with minimum/maximum specifications ultralow power: as low as 45 a in measurement mode and 0.1 a in standby mode at v s = 2.5 v (typical) power consumption scales automatically with bandwidth user-selectable resolution fixed 10-bit resolution full resolution, where resolution increases with g range, up to 13-bit resolution at 8 g (maintains 2 m g /lsb scale factor in all g ranges ) embedded, 32-level fifo buffer minimizes host processor load tap/double tap detection and free-fall detection activity/inactivity monitoring supply voltage range: 2.0 v to 3.6 v i/o voltage range: 1.7 v to v s spi (3- and 4-wire) and i 2 c digital interfaces flexible interrupt modes mappable to either interrupt pin measurement ranges selectable via serial command bandwidth selectable via serial command wide temperature range (?40c to +85c) 10,000 g shock survival pb-free/rohs compliant small and thin: 4 mm 3 mm 1.2 mm cavity lga package applications portable consumer devices high performance medical and industrial applications general description the high performance adxl350 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) and selectable measurement ranges up to 8 g . the adxl350 offers industry- leading noise and temperature performance for application robustness with minimal calibration. digital output data is formatted as 16-bit twos complement and is accessible through either a spi (3- or 4-wire) or i 2 c digital interface. the adxl350 is well suited for high performance portable applications. it measures the static acceleration of gravity in tilt- sensing applications, as well as dynamic acceleration resulting from motion or shock. its high resolution (2 m g /lsb) enables measurement of inclination changes of less than 1.0. several special sensing functions are provided. activity and inactivity sensing detect the presence or lack of motion and if the acceleration on any axis exceeds a user-set level. tap sensing detects single and double taps. free-fall sensing detects if the device is falling. these functions can be mapped to one of two interrupt output pins. low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. the adxl350 is supplied in a small, thin, 3 mm 4 mm 1.2 mm, 16-lead cavity laminate package. functional block diagram 3-axis sensor sense electronics digital filter adxl350 power management control and interrupt logic serial i/o int1 v s v dd i/o int2 sda/sdi/sdio sdo/alt address scl/sclk gnd adc 32 level fifo cs 10271-001 figure 1.
adxl350 data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 package information .................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 14 power sequencing ...................................................................... 14 power savings .............................................................................. 15 serial communications ................................................................. 16 spi ................................................................................................. 16 i 2 c ................................................................................................. 19 interrupts ..................................................................................... 21 fifo ............................................................................................. 21 self - te st ....................................................................................... 22 register map ................................................................................... 23 register definitions ................................................................... 24 appli cations information .............................................................. 28 power supply decoupling ......................................................... 28 mechanical considerations for mounting .............................. 28 tap detection .............................................................................. 28 threshold .................................................................................... 29 link mode ................................................................................... 29 sleep mode vs. low power mode ............................................. 29 offset calibration ....................................................................... 29 using self - te st ............................................................................ 30 axes of acceleration sensitivity ............................................... 32 layout and design recommendations ................................... 33 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 9 /12 rev ision 0 : initial version
data sheet adxl350 rev. 0 | page 3 of 36 specifications t a = 25c, v s = 2.5 v, v dd i/o = 2.5 v, acceleration = 0 g , and c io = 0.1 f, unless othe rwise noted. all minimum and maximum specifications are guaranteed. typical specifications are not guaranteed . table 1 . parameter test conditions min typ max unit sensor input each axis measurement range user selectable 1, 2, 4, 8 g nonlinearity percentage of full scale 0.5 % inter - axis alignment error 0.1 degrees cross - axis sensitivity 1 3 % output resolution each axis all g ranges 10 - bit resolution 10 bits 1 g range full resolution 10 bits 2 g range full resolution 11 bits 4 g range full resolution 12 bits 8 g range full resolution 13 bits sensitivity each axis sensitivity at x out , y out , z out any g - range, full resolution 473.6 512 550.4 lsb/ g scale factor at x out , y out , z ou t any g - range, full resolution 1.80 1.95 2.10 m g/ lsb sensitivity at x out , y out , z out 1 g , 10 - bit resolution 473.6 512 550.4 lsb/ g scale factor at x out , y out , z out 1 g , 10 - bit resolution 1.80 1.95 2.10 m g/ lsb sensitivity at x out , y out , z out 2 g , 1 0 - bit resolution 236.8 256 275.2 lsb/ g scale factor at x out , y out , z out 2 g , 10 - bit resolution 3.61 3.91 4.21 m g/ lsb sensitivity at x out , y out , z out 4 g , 10 - bit resolution 118.4 128 137.6 lsb/ g scale factor at x out , y out , z out 4 g, 10 - bit resoluti on 7.22 7.81 8.40 m g/ lsb sensitivity at x out , y out , z out 8 g, 10 - bit resolution 59.2 64 68.8 lsb/ g scale factor at x out , y out , z out 8 g, 10 - bit resolution 14.45 15.63 16.80 m g/ lsb sensitivity change due to temperature 0.01 %/c 0 g bias level e ach axis 0 g output for x out , y out ? 150 50 +150 m g 0 g output for z out ? 250 75 +250 m g 0 g offset vs. temperature (x a xis and y axi s) 2 ? 0.31 0.17 +0.31 m g /c 0 g offset vs. temperature (z a xis) 2 ? 0.49 0.24 +0.49 m g /c noise performance noise (x - axis and y - axi s) 100 hz data rate, full resolution 1.1 lsb rms noise (z - axi s) 100 hz data rate, full resolution 1.7 lsb rms output data rate and bandwidth user selectable measurement rate 3 6.25 3200 hz self - test 4 data rate 100 hz, 2.0 v v s 3.6 v output change in x - axis 0.2 2.1 g output change in y - axis ? 2.1 ? 0.2 g output change in z - axis 0.3 3.4 g power supply operating voltage range (v s ) 2.0 2.5 3.6 v interface voltage range (v dd i/o ) 1.7 1.8 v s v supply current data rate > 100 hz 1 66 a data rate < 10 hz 45 a standby mode leakage current 0.1 2 a turn - on time 5 data rate = 3200 hz 1.4 ms operating temperature range ? 40 +85 o c 1 cross - axis sensitivity is defined as coupling between any two axes. 2 offset vs. temperature minimum/maximum specifications are guaranteed by characterization and represent a m ean 3 distribution. 3 bandwidth is half the output data rate. 4 self - test change is defined as the output ( g ) when the self_test bit = 1 (in the data_format register) minus the output (g ) when the self_test bit = 0 (in the data_format register). due to d evice filtering, the output reaches its final value after 4 when enabling or disabling self - test, where = 1/(data rate). 5 turn - on and wake - up times are determined by the user - defined bandwidth. at a 100 hz data rate, the turn - on and wake - up times ar e each approximately 11.1 ms. for other data rates, the turn - on and wake - up times are each approximately + 1.1 in milliseconds, where = 1/(data rate).
adxl350 data sheet rev. 0 | page 4 of 36 absolute maximum rat ings table 2 . parameter rating acceleration any axis, unpowered 10,000 g any axis, powered 10,000 g v s ? 0.3 v to +3.6 v v dd i/o ? 0.3 v to +3.6 v digital pins ? 0.3 v to v dd i/o + 0.3 v or 3.6 v, whichever is less all other pins ? 0.3 v to +3.6 v output shor t - circuit duration (any pin to ground) indefinite temperature range powered ? 40c to +105c storage ? 40c to +105c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; fu nctional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ther mal resistance table 3 . package characteristics package type ja jc device weight 16- terminal lga _cav 150c/w 85c/w 20 mg package information the information in figure 2 and table 4 provide details about the package branding for the adxl350 . for a complete listing of product availability, see the ordering guide section. xl350b ywvvvv 10271-202 figure 2. product information on package (top view ) table 4 . package branding information branding key field description xl350b part identifier for adxl350 yw date code vvvv factory lot code esd caution
data sheet adxl350 rev. 0 | page 5 of 36 pin configuration an d function descripti ons reserved gnd v s sdo/ alt address sda/sdi/sdio cs nc = n o i n te rna l c o nn e c tio n nc v dd i/o nc scl/sclk nc reserved gnd int1 reserved int2 top view adxl350 (not to scale) 1 2 3 4 5 13 12 11 10 9 6 7 8 16 15 14 +z +x +y 10271-002 figure 3 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 v dd i/o digital interface supply voltag e. 2 nc not internally connected . 3 nc not internally connected . 4 scl/sclk serial communications clock . 5 nc not internally connected . 6 sda/sdi/sdio serial data (i 2 c)/serial data input (spi 4 - wire)/serial data input and output (spi 3 - wire) . 7 sdo/alt address serial data output/alternate i 2 c address select . 8 cs chip select . 9 int2 interrupt 2 output . 10 reserved reserved. this pin must be connect ed to ground or left open. 11 int1 interrupt 1 output . 12 reserved reserved. this pin must be connect ed to ground. 13 gnd this pin m ust be connected to ground. 14 v s supply voltage . 15 reserved reserved. this pin must be connected to v s or left open. 16 gnd this pin m ust be connected to ground.
adxl350 data sheet rev. 0 | page 6 of 36 typical performance characteristics n = 460 for all typical performance characteristics plots, unless otherwise noted . 0 ?100 ?80 ?60 ?40 ?20 0 zero g offset (m g) 20 40 60 80 100 10 20 30 40 percent of population (%) 10271-103 figure 4. x - axis zero g offset at 25c, v s = 2.5 v 0 ?100 ?80 ?60 ?40 ?20 0 zero g offset (m g) 20 40 60 80 100 10 20 30 40 percent of population (%) 10271-104 figure 5. y - axis zero g offset at 25c, v s = 2.5 v zero g offset (m g) 0 20 10 30 ?125 ?105 ?85 ?65 ?45 ?25 ?5 15 35 55 75 95 1 15 percent of popul a tion (%) 10271-105 figure 6. z - axis zero g offset at 25c, v s = 2.5 v 0 ?100 ?80 ?60 ?40 ?20 0 zero g offset (m g) 20 40 60 80 100 10 20 30 percent of population (%) 10271-106 figur e 7. x - axis zero g offset at 25c, v s = 3.0 v 0 ?100 ?80 ?60 ?40 ?20 0 zero g offset (m g) 20 40 60 80 100 10 20 30 percent of population (%) 10271-107 figure 8. y - axis zero g offset at 25c, v s = 3. 0 v 0 10 20 30 ?150 ?130 ? 1 10 ?90 ?70 ?50 ?30 ?10 10 30 50 70 ?230 ?210 ?190 ?170 percent of popul a tion (%) zero g offset (m g) 10271-108 figure 9. z - axis zero g offset at 25c, v s = 3. 0 v
data sheet adxl350 rev. 0 | page 7 of 36 0 10 20 30 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271-109 figure 10 . x - axis zero g offset temperature coefficient, v s = 2.5 v 0 10 20 30 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271- 1 10 figure 11 . y - axis zero g offset temperature coefficient, v s = 2.5 v 0 10 5 15 20 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271- 11 1 figure 12 . z - axis zero g offset temperature coefficient, v s = 2.5 v ?100 ?50 ?25 ?75 0 50 75 25 100 ?60 ?40 ?20 0 20 40 60 80 100 output (m g) temper a ture (c) n = 1 6 v s = v dd i/o = 2 . 5 v 10271- 1 12 figure 13 . x - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 2.5 v ?60 ?40 ?20 0 20 40 60 80 100 ?100 ?50 ?25 ?75 50 75 25 0 100 output (m g) temper a ture (c) n = 1 6 v s = v dd i/o = 2 . 5 v 10271- 1 13 figure 14 . y - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 2.5 v ?60 ?40 ?20 0 20 40 60 80 100 ?150 ?100 ?50 0 50 100 150 output (m g) temper a ture (c) n = 1 6 v s = v dd i/o = 2 . 5 v 10271- 1 14 figure 15 . z - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 2.5 v
adxl350 data sheet rev. 0 | page 8 of 36 0 10 20 30 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271- 1 15 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 figure 16 . x - axis zero g offse t temperature coefficient , v s = 3.0 v 0 10 20 30 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271- 1 16 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 figure 17 . y - axis zero g offset temperature coefficient , v s = 3.0 v 0 5 15 10 20 percent of popul a tion (%) zero g offset temper a ture coefficient (m g /c) ?40c to +25c +25c to +85c 10271- 1 17 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 figure 18 . z - axis zero g offset temperature coefficient , v s = 3.0 v ?100 ?50 ?25 ?75 50 75 25 0 100 ?20 ?40 ?60 0 20 40 60 80 100 output (m g) temper a ture (c) n = 1 6 v s = v dd i/o = 3.0v 10271- 1 18 figure 19 . x - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 3.0 v ?20 ?40 ?60 0 20 40 60 80 100 ?100 ?50 ?25 ?75 50 75 25 100 0 output (m g) temper a ture (c) 10271- 1 19 n = 1 6 v s = v dd i/o = 3.0v fig ure 20 . y - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 3.0 v ?150 ?100 ?50 0 50 100 150 ?20 ?40 ?60 0 20 40 60 80 temper a ture (c) 10271-120 output (m g) n = 1 6 v s = v dd i/o = 3.0v figure 21 . z - axis zero g offset vs. temperature 16 parts soldered to pcb, v s = 3.0 v
data sheet adxl350 rev. 0 | page 9 of 36 0 20 40 60 470 475 480 485 490 495 500 505 510 515 520 525 530 535 540 545 550 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-121 figure 22 . x - axis sensitivity at 25c, v s = 2.5 v , full resolution 0 20 40 60 470 475 480 485 490 495 500 505 510 515 520 525 530 535 540 545 550 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-122 figure 23 . y - axis sensitivity at 25c, v s = 2.5 v , full resolution 0 20 40 60 470 475 480 485 490 495 500 505 510 515 520 525 530 535 540 545 550 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-123 figure 24 . z - axis sensitivity at 25c, v s = 2.5 v , full resolution percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-124 0 20 40 60 80 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 25 . x - axis sensitivity temperature coefficient , v s = 2.5 v percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-125 0 20 40 60 80 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 26 . y - axis sensitivity temperature coefficient , v s = 2.5 v percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-126 0 10 20 30 40 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 27 . z - axis sensitivity temperat ure coefficient , v s = 2.5 v
adxl350 data sheet rev. 0 | page 10 of 36 0 20 40 10 30 555 560 565 570 575 495 500 505 510 515 520 525 530 535 540 545 550 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-127 figure 28 . x - axis sensitivity, v s = 3.0 v , full resolution 555 560 565 570 575 495 500 505 510 515 520 525 530 535 540 545 550 0 60 20 40 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-128 figure 29 . y - axis sensitivity, v s = 3.0 v , full resolution 0 60 20 40 470 475 480 485 490 495 500 505 510 515 520 525 530 535 540 545 550 percent of popul a tion (%) sensitivit y (lsb/ g) 10721-129 figure 30 . z - axis sensi tivity, v s = 3.0 v , full resolution percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-130 0 20 40 60 80 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 31 . x - axis sensitivity temperature coefficient , v s = 3.0 v percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-131 0 20 40 60 10 30 50 70 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 32 . y - axis sensitivity temperature coefficient , v s = 3.0 v percent of popul a tion (%) sensitivit y temper a ture coefficient (%/c) ?40c to +25c +25c to +85c 10271-132 0 20 40 10 30 50 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 figure 33 . z - axis sensitivity temperature coefficient , v s = 3.0 v
data sheet adxl350 rev. 0 | page 11 of 36 490 495 500 505 510 515 520 525 530 535 540 ?60 ?40 ?20 0 20 40 60 80 100 sensitivity (lsb/ g) temperature (c) n = 16 v s = v dd i/o = 2.5v 10271-133 figure 34 . x - axis sensitivity vs. temperature 16 parts soldered to pcb, v s = 2.5 v , full resolution ?60 ?40 ?20 0 20 40 60 80 100 490 495 500 505 510 515 520 525 530 535 540 sensitivity (lsb/ g) temperature (c) 10271-134 n = 16 v s = v dd i/o = 2.5v figure 35 . y - axis sensitivity vs . temperature 16 parts soldered to pcb, v s = 2.5 v , full resolution ?60 ?40 ?20 0 20 40 60 80 100 490 495 500 505 510 515 520 525 530 535 540 sensitivity (lsb/ g) temperature (c) 10271-135 n = 16 v s = v dd i/o = 2.5v figure 36 . z - axis sensitivity vs. temperature 16 parts soldered to pcb, v s = 2.5 v , full resolution 500 505 510 515 520 525 530 535 540 545 550 ?60 ?40 ?20 0 20 40 60 80 100 sensitivity (lsb/ g) temperature (c) 10271-136 n = 16 v s = v dd i/o = 3.0v figure 37 . x - axis sensitivit y vs. temperature 16 parts soldered to pcb, v s = 3.0 v , full resolution ?60 ?40 ?20 0 20 40 60 80 100 500 505 510 515 520 525 530 535 540 545 550 sensitivity (lsb/ g) temperature (c) 10271-137 n = 16 v s = v dd i/o = 3.0v figure 38 . y - axis sensitivity vs. temperature 16 parts soldered to pcb, v s = 3.0 v , full resolution ?60 ?40 ?20 0 20 40 60 80 100 sensitivity (lsb/ g) temperature (c) 10271-138 490 495 500 505 510 515 520 525 530 540 550 535 545 n = 16 v s = v dd i/o = 3.0v figure 39 . z - axis sensit ivity vs. temperature 16 parts soldered to pcb, v s = 3.0 v , full resolution
adxl350 data sheet rev. 0 | page 12 of 36 0 20 40 60 80 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 percent of popul a tion (%) output ( g) 10271-139 figure 40 . x - axis self - test response at 25c, v s = 2.5 v 0 20 40 60 percen t age of popul a tion (%) output ( g) ?1.00 ?0.95 ?0.90 ?0.85 ?0.80 ?0.75 ?0.70 ?0.65 ?0.60 10271-140 figure 41 . y - axis self - test response at 25c, v s = 2.5 v 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 percent of popul a tion (%) output ( g) 10271-141 0 20 40 60 fig ure 42 . z - axis self - test response at 25c, v s = 2.5 v 0 20 40 60 80 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 percent of popul a tion (%) output ( g) 10271-142 figure 43 . x - axis self - test response at 25c, v s = 3.0 v 0 20 40 80 60 100 ?1.20 ?1.15 ?1.10 ?1.05 ?1.00 ?0.95 ?0.90 ?0.85 ?0.80 percent of popul a tion (%) output ( g) 10271-143 figure 44 . y - axis self - test response at 25c, v s = 3.0 v 0 10 20 40 30 50 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 percent of popul a tion (%) output ( g) 10271-144 f igure 45 . z - axis self - test response at 25c, v s = 3.0 v
data sheet adxl350 rev. 0 | page 13 of 36 0 20 40 60 percent of popul a tion (%) current consumption (a) 100 1 10 120 130 140 150 160 170 180 190 200 10271-145 figure 46 . current consumption at 25c, 100 hz output data rate, v s = 2.5 v, 31 parts 0 20 40 60 80 100 120 140 160 180 1 10 100 1k 10k current (a) output d at a r a te (hz) 10271-146 figure 47 . current consumption vs. output data rate at 25c v s = 2.5 v, 10 parts 100 120 140 160 180 200 220 2 3 4 current (a) supp l y vo lt age (v) 10271-147 figure 48 . supply current vs. supply voltage, v s at 25c , 10 parts
adxl350 data sheet rev. 0 | page 14 of 36 theory of operation the adxl350 is a complete 3 - axis acce leration measurement system with a selectable measurement range of 1 g, 2 g, 4 g , or 8 g . it measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, which allows the device to be used as a tilt sensor . the sensor is a polysilicon surface - micromachined structure built on top of a silicon wafer. polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. deflection of the structure is me asured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. acceleration deflects the beam and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. phase - sensitive demodulation is used to determine the magnitude and polarity of the acceleration. power sequencing power can be applied to v s or v dd i/o in any sequence without damaging the adxl3 50 . all possible power - on modes are summarized in table 6 . th e interface voltage level is set with the interface supply volt - age , v dd i/o , which must be present to ensure that the ad xl350 does not create a conflict on the communication bus. for single - supply operation, v dd i/o can be the same as the main supply, v s . in a dual - supply application, however, v dd i/o can differ from v s to accommodate the desired interface voltage , as long as v s is greater than v dd i/o . after v s is applied, the device enters standby mode, where power consumption is minimized and the device waits for v dd i/o to be applied and for the command to enter measurement mode to be received. (this command can be ini tiated by setting the measure bit in the power_ctl register (address 0x2d).) in addition, any register can be written to or read from to configure the part while the device is in standby mode. it is recommended to configure the device in standby mode and t hen to enable measurement mode. clearing the measure bit returns the device to the standby mode. table 6 . power sequencing condition v s v dd i/o description power off off off the device is completely off, but there is the potentia l for a communication bus conflict. bus disabled on off the device is on in standby mode, but communication is unavailable and create s a conflict on the communication bus. the duration of this state should be minimized during power - up to prevent a conflic t. bus enabled off on no functions are available, but the device does not create a conflict on the communication bus. standby or measurement on on at power - up, the device is in standby mode, awaiting a command to enter measurement mode, and all sensor fu nctions are off. after the device is instructed to enter measurement mode, all sensor functions are available.
data sheet adxl350 rev. 0 | page 15 of 36 power savings power modes the adxl350 automatically modulates its power consumption in proport ion to its output data rate, as outlined in table 7 . if additional power savings is desired, a lower power mode is available. in this mode, the internal sampling rate is reduced, allowing for power savings in the 1 2.5 hz to 400 hz data rate range but at the expense of slightly greater noise. to enter lower power mode, set the low_power bit (bit 4) in the bw_rate register (address 0x2c). the current consumption in low power mode is shown in table 8 for cases where there is an advantage for using low power mode. the current consump - tion values shown in table 7 and table 8 are for a v s of 2.5 v. current scales linearly with v s . table 7 . current consumption vs. data rate (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) output data rate (hz) bandwidth (hz) rate code i dd (a) 3200 1600 1111 145 1600 800 1110 100 800 400 1101 145 400 200 1100 145 200 100 1011 145 100 50 1010 145 50 25 1001 100 25 12.5 1000 65 12.5 6.25 0111 55 6.25 3.125 0110 40 table 8 . current consumption vs. data rate, low power mode (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) outpu t data rate (hz) bandwidth (hz) rate code i dd (a) 400 200 1100 100 200 100 1011 65 100 50 1010 55 50 25 1001 50 25 12.5 1000 40 12.5 6.25 0111 40 auto sleep mode additional power can be saved if the ad xl350 automatically switches to sleep mode during periods of inactivity. to enable this feature, set the thresh_inact register (address 0x25) and the time_inact register (address 0x26) each to a value that signifies inactivity (the appropriate value depen ds on the application), and then set the auto_sleep bit and the link bit in the power_ctl register (address 0x2d). current consumption at the sub - 8 hz data rates used in this mode is typically 40 a for a v s of 2.5 v. standby mode for even lower power ope ration, standby mode can be used. in standby mode, current consumption is reduced to 0.1 a (typical). in this mode, no measurements are made. standby mode is entered by clearing the measure bit (bit 3) in the power_ctl register (address 0x2d). placing the device into standby mode preserves the contents of fifo.
adxl350 data sheet rev. 0 | page 16 of 36 serial communication s i 2 c and spi digi tal communications are possible and regardless , the adxl350 always operates as a slave. i 2 c mode is enabled if the cs pin is tied high to v dd i/o . the cs pin should always be tied high to v dd i/o or be driven by an external controller because there is no default mode if the cs pin is left unconne cted. n ot taking thi s precaution may result in an inability to communicate with the part. in spi mode, the cs pin is controlled by the bus master. in both spi and i 2 c modes of operation, data transmitted from the adxl350 to the master device should be ignored during writes to the adxl350 . spi for spi, either 3 - or 4 - wire configuration is possible, as shown in the connection diagrams in figure 49 and figure 50. clearing the spi bit in the data_format register (address 0x31) selects 4 - wire mode, whereas setting the spi bit selects 3 - wire mode. the maximum spi clo ck speed is 5 mhz with 100 pf maximum loading, and the timing scheme follows clock polarity (cpol) = 1 and clock phase (cpha) = 1. cs is the serial port enable line and is controlled by the spi master. this line must go low at the sta rt of a transmission and high at the end of a transmission , as shown in figure 52 . sclk is the serial port clock and is supplied by the spi master. it is stopped high when cs is high during a period of no transmission. sdi and sdo are the serial data input and output, respectively. data should be sampled at the rising edge of sclk. processor d out d in/out d out adxl350 cs sdio sdo sclk 10271-004 figure 49 . 3 - wire spi connection diagram processor d out d out d in d out adxl350 cs sdi sdo sclk 10271-003 figure 50 . 4 - wire spi connection diagram to read or write multiple bytes in a single transmission, the multiple - byte bit, located after the r/ w bit in the first byte transfer (mb in figure 52 to figure 54 ), must be set. after the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the adxl350 to point to the next register for a read or write. this shifting continues until the clock pulses cease and cs is deasserted. to perform reads or writes on different, nonsequential registers, cs must be deasserted between transmissi ons and the new register must be addressed separately. the timing diagram for 3 - wire spi reads or writes is shown in figure 54 . the 4 - wire equivalents for spi writes and reads are shown in figure 52 and figure 53, respectively. preventing bus traffic errors the adxl350 cs pin is used both for initiating spi transac t - tions, and for enabling i 2 c mode. when th e adxl350 is used on a n spi bus with multiple devices, its cs pin is held high while the master communicates with the other devices. there may b e conditions where a n spi command transmitted to another device looks like a valid i 2 c comma nd. in this case, the adxl350 would interpret this as an attempt to communicate in i 2 c mode, and could interfere with other bus traffic. unless bus traffic can be adequately controlled to assure such a condition never occurs, it is recommended to add a logic gate in front of the sdi pin as shown in figure 51 . this or gate will hold the sda line high when cs is high to preven t spi bus traffic at the adxl350 from appearing as an i 2 c start command. processor d out d in/out d out adxl350 cs sdio sdo sclk 10271-151 figure 51 . recommended spi connection diagram when us ing multiple spi devices on a single bus adxl350 adxl350 adxl350
data sheet adxl350 rev. 0 | page 17 of 36 table 9 . spi digital input/output voltage limit 1 parameter test conditions min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level input current (i il ) v in = v dd i/o 0.1 a high level input current (i ih ) v in = 0 v ? 0.1 a digital output low level output voltage (v ol ) i ol = 10 ma 0.2 v dd i/o v high level output voltage (v oh ) i oh = ?4 ma 0.8 v dd i/o v low level output current (i ol ) v ol = v ol, max 10 ma high level output current (i oh ) v oh = v oh, min ? 4 ma pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf 1 limits based on characterization results, not production tested. table 10 . spi timing (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) 1 limit 2 , 3 parameter min max unit description f sclk 5 mhz spi clock frequency t sclk 200 ns 1/(spi c lock frequency) mark - space ratio for the sclk input is 40/60 to 60/40 t delay 10 ns cs falling edge to sclk falling edge t quiet 10 ns sclk rising edge to cs rising edge t dis 100 ns cs ri sing edge to sdo disabled t cs,dis 250 ns cs deassertion between spi communications t s 0.4 t sclk ns sclk low pulse width (space) t m 0.4 t sclk ns sclk high pulse width (mark) t sdo 95 ns sclk falling edge to sdo tra nsition t setup 10 ns sdi valid before sclk rising edge t hold 10 ns sdi valid after sclk rising edge 1 the cs , sclk, sdi, and sdo pins are not internally pulled up or down; they must be driven for proper operation. 2 limits are based on characterization results, characterized with f sclk = 5 mhz and bus load capacitance of 100 pf; not production tested. 3 the timing values are measured corresponding to the input thresholds (v il and v ih ) given in table 9 .
adxl350 data sheet rev. 0 | page 18 of 36 t delay t setup t hold t sdo x x x w mb a5 a0 d7 d0 x x x address bits data bits t sclk t m t s t quiet t dis t cs,dis sclk sdi sdo cs 10271-017 figure 52 . spi 4 - wire write cs x x x r mb a5 a0 d7 d0 x x x address bits data bits t dis sclk sdi sdo t quiet t cs,dis t sdo t setup t hold t delay t sclk t m t s 10271-018 figure 53 . spi 4 - wire read cs t delay t setup t hold t sdo r/w mb a5 a0 d7 d0 address bits data bits t sclk t m t s t quiet t cs,dis sclk sdio sdo notes 1. t sdo is only present during reads. 10271-019 figure 54 . spi 3 - wire read/write
data sheet adxl350 rev. 0 | page 19 of 36 i 2 c with cs tied high to v dd i/o , the adxl350 is in i 2 c mode, requiring a simple 2 - wire connection as shown in figure 55. the adxl350 conforms to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007, available from nxp semiconductor. it supports standard (100 khz) and fast (400 khz) data transfer m odes if the timing parameters given in table 12 and figure 57 are met. single - b yte or multiple - byte reads/writes are supported, as shown in figure 56 . with the sdo /alt address pin (pin 7) high, the 7 - bit i 2 c address for the device is 0x1d, followed by the r/ w bit. this translates to 0x3a for a write and 0x3b for a read. an alternate i 2 c address of 0x53 (follo wed by the r/ w bit) can be chosen by grounding the sdo /alt address pin (pin 7 ). this translates to 0xa6 for a write and 0xa7 for a read. if other devices are connected to the same i 2 c bus, the nominal operating voltage level of the se other devices cannot exceed v dd i/o by more than 0.3 v. external pull - up resistors, r p , are necessary for proper i 2 c operation. refer to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007, when selecting pull - up resistor values to e nsure proper operation. table 11. i 2 c digital input/output voltage parameter limit 1 unit digital input voltage low level input voltage (v il ) 0.25 v dd i/o v max high level input voltage (v ih ) 0.75 v dd i/o v min digital outp ut voltage low level output voltage (v ol ) 2 0.2 v dd i/o v max 1 limits are based on characterization results; not production tested. 2 the limit given is only for v dd i/o < 2 v. when v dd i/o > 2 v, the limit is 0.4 v maximum. processor d in/out d out r p v dd i/o r p adxl350 cs sda alt address scl 10271-008 figure 55 . i 2 c connection diagram (address 0x53) 10271-009 notes 1. this start is either a restart or a stop followed by a start. 2. the shaded areas represent when the device is listening. master start slave address + write register address slave ack ack ack master start slave address + write register address slave ack ack ack ack master start slave address + write register address stop slave ack ack master start start 1 start 1 slave address + write register address nack stop slave ack ack data stop ack single-byte write multiple-byte write data data multiple-byte read slave address + read slave address + read ack data data data stop nack ack single-byte read figure 56 . i 2 c device addressing adxl350
adxl350 data sheet rev. 0 | page 20 of 36 table 12. i 2 c timing (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) limit 1 , 2 parameter min max unit description f scl 400 khz scl clock frequency t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd, sta , start/repeated s tart condition hold time t 5 350 ns t su, dat , data setup time t 6 3 , 4 , 5 , 6 0 0.65 s t hd, dat , data hold time t 7 0.6 s t su, sta , setup time for repeated start t 8 0.6 s t su, sto , stop condition setup time t 9 1.3 s t buf , bus - free time betwe en a stop condition and a start condition t 10 300 ns t r , rise time of both scl and sda when receiving 0 ns t r , rise time of both scl and sda when receiving or transmitting t 11 250 ns t f , fall time of sda when receiving 300 ns t f , fall time of both scl and sda when transmitting 20 + 0.1 c b 7 ns t f , fall time of both scl and sda when transmitting or receiveing c b 400 pf capacitive load for each bus line 1 limits are based on characterization results, with f scl = 400 khz and a 3 ma sink current; not production tested. 2 all values are referred to the v ih and the v il levels given in table 11. 3 t 6 is the data hold time that is measured from the falling edge of scl. it applies to data in transmission and acknowledge times . 4 a transmitting device must internally provide an output hold time of at least 300 ns for the sd a signal (with respect to v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. 5 the maximum t 6 value must be met only if the device does not stretch the low period (t 3 ) of the scl signal. 6 the maximum value for t 6 is a f unction of the clock low time (t 3 ), the clock rise time (t 10 ), and the minimum data setup time (t 5(min) ). this value is calculated as t 6(max) = t 3 ? t 10 ? t 5(min) . 7 c b is the total capacitance of one bus line in picofarads. sda t 9 scl t 3 t 10 t 1 1 t 4 t 4 t 6 t 2 t 5 t 7 t 1 t 8 st art condition repe a ted st art condition st op condition 10271-020 figure 57 . i 2 c timing diagram
data sheet adxl350 rev. 0 | page 21 of 36 interrupts the adxl350 provides two output pins for driving interrupts: int1 and int2. each interrupt function is described in detail in this section. all functions can be used simultaneously, with the only limiting feature being tha t some functions may need to share interrupt pins. interrupts are enabled by setting the appropriate bit in the int_enable register (address 0x2e) and are mapped to either the int1 o r int2 pin based on the contents of the int_map register (address 0x2f). it is recom - mended that interrupt bits be configured with the interrupts disabled, preventing interrupts from being accidentally triggered during configuration. this can be done by writing a value of 0x00 to the int_enable register. clearing interrupts is performed either by reading the data registers ( address 0x32 to address 0x37) until the interrupt condition is no longer valid for the data - related interrupts or by reading the int_source register ( address 0x30) for the remaining interrupts. this section describes the interrupts that can be set in the int_enable register and monitored in the int_source register. data_ready the data_ready bit is set when new data is available and is cleared when no new data is available. single_tap the single_tap bit is set when a single acceleration event that is greater than the value in the thresh_tap register (address 0x1d) occurs for less time than is specified in the dur register (address 0x21). double _tap the double_tap bit is set when two acceleration events that ar e greater than the value in the thresh_tap register (address 0x1d) occur for less time than is specified in the dur register (address 0x21), with the second tap starting after the time specified by the latent register (address 0x22) but within the time spe cified in the window register (address 0x23). see the tap detection section for more details. activity the activity bit is set when acceleration greater than the value stored in the thresh_act register (address 0x2 4) is experienced. inactivity the inactivity bit is set when acceleration of less than the value stored in the thresh_inact register (address 0x25) is experi - enced for more time than is specified in the time_inact register (address 0x26). the maximum value for time_inact is 255 sec. free_fall the free_fall bit is set when acceleration of less than the value stored in the thresh_ff register (address 0x28) is experienced for more time than is specified in the time_ff register (address 0x29). the free_fall int errupt differs from the inactivity interrupt as follows: all axes always participate, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc - coupled. watermark the watermark bit is set when the number of samples in fif o equals the value stored in the samples bits (register fifo_ctl, address 0x38). the watermark bit is cleared automatically when fifo is read, and the content returns to a value below the value stored in the samples bits. overrun the overrun bit is set whe n new data replaces unread data. the precise operation of the overrun function depends on the fifo mode. in bypass mode, the overrun bit is set when new data replaces unread data in the datax, datay, and dataz registers ( address 0x32 to address 0x37). in all other modes, the overrun bit is set when fifo is filled. the overrun bit is automatically cleared when the contents of fifo are read. fifo the adxl350 contains patent pending technology for an embedded 32 - level fifo that can be used to minimize host processor burden. this buffer has four modes: bypass, fifo, stream, and trigger (see table 20 ). each mode is selected by the settings of the fifo_mode bits in the fifo_ ctl register (address 0x38). bypass mode in bypass mode, fifo is not operational and, therefore, remains empty. fifo mode in fifo mode, data from measurements of the x - , y - , and z - axes are stored in fifo. when the number of samples in fifo equals the leve l specified in the samples bits of the fifo_ctl register (address 0x38), the watermark interrupt is set. fifo continues accumulating samples until it is full (32 samples from measurements of the x - , y - , and z - axes) and then stops collecting data. after fif o stops collecting data, the device continues to operate; therefore, features such as tap detection can be used after fifo is full. the watermark interrupt continues to occur until the number of samples in fifo is less than the value stored in the samples bits of the fifo_ctl register. stream mode in stream mode, data from measurements of the x - , y - , and z - axes are stored in fifo. when the number of samples in fifo equals the level specified in the samples bits of the fifo_ctl register (address 0x38) , the watermark interrupt is set. fifo continues accumulating samples and holds the latest 32 samples from measurements of the x - , y - , and z - axes, discarding older data as new data arrives. the watermark interrupt continues occurring until the number of samples in fifo is less than the value stored in the samples bits of the fifo_ctl register.
adxl350 data sheet rev. 0 | page 22 of 36 trigger mode in trigger mode, fifo accumulates samples, holding the latest 32 samples from measurements of the x - , y - , and z - axes. after a trigger event occurs and an inte rrupt is sent to the int1 or int2 pin (determined by the trigger bit in the fifo_ctl register), fifo keeps the last n samples (where n is the value specified by the samples bits in the fifo_ctl register) and then operates in fifo mode, collecting new sampl es only when fifo is not full. a delay of at least 5 s should be present between the trigger event occurring and the start of reading data from the fifo to allow the fifo to discard and retain the necessary samples. additional trigger events cannot be re cognized until the trigger mode is reset. to reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. note that the fifo data should be read first because placing the device into bypass mode clears fifo. retrievin g data from fifo the fifo data is read through the datax, datay, and dataz registers ( address 0x32 to address 0x37). when the fifo is in fifo, stream, or trigger mode, reads to the datax, datay, and dataz registers read data stored in the fifo. each time d ata is read from the fifo, the oldest x - , y - , and z - axes data are placed into the datax, datay , and dataz registers. if a single - byte read operation is performed, the remaining bytes of data for the current fifo sample are lost. therefore, all axes of int erest should be read in a burst (or multiple - byte) read operation. to ensure that the fifo has completely popped (that is, that new data has completely moved into the datax, datay, and dataz registers), there must be at least 5 s between the end of reading the data registers and the start of a new read of the fifo or a read of the fifo_status register (address 0x39) . the end of reading a data register is signified by the transition from register 0x37 to register 0x38 or by the cs pin going high. for spi operation at 1.6 mhz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the fifo has completely popped. for spi o peration greater than 1.6 mhz, it is necessary to deassert the cs pin to ensure a total delay of 5 s; otherwise, the delay will not be sufficient. the total delay necessary for 5 mhz operation is at most 3.4 s. this is not a concern when using i 2 c mode because the communication rate is low enough to ensure a sufficient delay between fifo re ads. self - test the adxl350 incorporates a self - test feature that effectively tests its mechanical and electronic systems simultaneously. when the self - test function is enabled (via the self_test bit in the d ata_format register, address 0x31), an electrostatic force is exerted on the mechanical sensor. this electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the devi ce. this added electrostatic force results in an output change in the x - , y - , and z - axes. because the electrostatic force is proportional to v s 2 , the output change varies with v s . the self - test feature of the adxl350 also exhibits a bimodal behavior that depends on which phase of the clock self - test is enabled. however, the limits shown in table 1 and table 13 to table 16 are valid for all potential self - test values across the entire allowable voltage range. use of the self - test feature at data rates less than 100 hz may yield values outside these limits. therefore, the part should be placed into a dat a rate of 100 hz or greater when using self - test. table 13. self - test output in lsb for 1 g , 1 0 - bit resolution or a ny g -r ange, full resolution axis min max unit x 100 1180 lsb y ? 1180 ? 100 lsb z 150 1850 lsb table 14. self - test output in lsb for 2 g , 1 0 - bit resolution axis min max unit x 50 590 lsb y ? 590 ? 50 lsb z 75 925 lsb table 15. self - test output in lsb for 4 g , 10 - bit resolution axis min max unit x 25 295 lsb y ? 2 95 ? 25 lsb z 38 4 63 lsb table 16. self - test output in lsb for 8 g , 10 - bit resolution axis min max unit x 12 1 48 lsb y ? 1 48 ? 12 lsb z 19 2 32 lsb
data sheet adxl350 rev. 0 | page 23 of 36 register map table 17 . register map address hex dec name type reset value description 0x0 0 0 devid r 11100101 device id. 0x0 1 to 0x0 1c 1 to 28 reserved reserved. do not access. 0x 1d 29 thresh_tap r/ w 00000000 tap threshold. 0x 1 e 30 ofsx r/ w 00000000 x - axis offset. 0x 1f 31 ofsy r/ w 00000000 y - axis offset. 0x 20 32 ofsz r/ w 00000000 z - axis offset. 0x 21 33 dur r/ w 00000000 tap duration. 0x 22 34 latent r/ w 00000000 tap latency. 0x 23 35 window r/ w 00000000 tap window. 0x 24 36 thresh_act r/ w 00000000 activity threshold. 0x 25 37 thresh_inact r/ w 00000000 ina ctivity threshold. 0x 26 38 time_inact r/ w 00000000 inactivity time. 0x 27 39 act_inact_ctl r/ w 00000000 axis enable control for activity and inactivity detection. 0x 28 40 thresh_ff r/ w 000 00000 free - fall threshold. 0x 29 41 time_ff r/ w 00000000 free - fall time. 0x 2a 42 tap_axes r/ w 00000000 axis control for tap/double tap. 0x 2b 43 act_tap_status r 00000000 source of tap/double tap. 0x 2c 44 bw_ra te r/ w 00001010 data rate and power mode control. 0x 2d 45 power_ctl r/ w 00000000 power - saving features control. 0x 2e 46 int_enable r/ w 00000000 interrupt enable control. 0x 2f 47 int_map r / w 00000000 interrupt mapping control. 0x 30 48 int_source r 00000010 source of interrupts. 0x 31 49 data_format r/ w 00000000 data format control. 0x 32 50 datax0 r 00000000 x - axis data 0. 0x 33 51 datax1 r 00000 000 x - axis data 1. 0x 34 52 datay0 r 00000000 y - axis data 0. 0x 35 53 datay1 r 00000000 y - axis data 1. 0x 36 54 dataz0 r 00000000 z - axis data 0. 0x 37 55 dataz1 r 00000000 z - axis data 1. 0x 38 56 fifo_ctl r/ w 00000000 fifo control. 0 x 39 57 fifo_status r 00000000 fifo status.
adxl350 data sheet rev. 0 | page 24 of 36 register definitions register 0x00 devid (read only) d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 0 0 1 0 1 the devid register holds a fixed device id code of 0xe5 (345 octal). register 0x1d thresh_tap (read/write) the thr esh_tap register is eight bits and holds the threshold value for tap interrupts. the data format is unsigned, so the magnitude of the tap event is compared with the value in thresh_tap . the scale factor is 31.2 m g /lsb (that is, 0xff = + 8 g ). a value of 0 may result in und esirable behavior if tap/ double tap interrupts are enabled. register 0x1e, register 0x1f, register 0x20 ofsx, ofsy, ofsz (read/write) the ofsx, ofsy, and ofsz registers are each eight bits and offer user - set offset adjustments in twos co mplement format with a scale factor of 7.8 m g /lsb (that is, 0x7f = +1 g ). register 0x21 dur (read/write) the dur register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the thresh_tap threshold t o qualify as a tap event. the scale factor is 625 s/lsb. a value of 0 disables the tap/double tap functions. register 0x22 latent (read/write) the latent register is eight bits and contains an unsigned time value representing the wait time from the detect ion of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. the scale factor is 1.25 ms/lsb. a value of 0 disables the double tap function. register 0x23 window (read/write) the window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. the scale factor is 1.25 ms/lsb. a value of 0 disables the double tap function. register 0x24 thresh_act (read/write) the thresh_act register is eight bits and holds the threshold value for detecting activity. the data format is unsigned, so the magnitude of the activity event is compared with the value in the thresh_act register . the scale factor is 31.2 m g /lsb. a value of 0 may result in undesirable behavior if the activity interrupt is enabled. register 0x25 thresh_inact (read/write) the thresh_inact register is eight bits and holds the threshold value for detecting inactivity. the data format is unsigned, so the magnitude of the inactivity event is compared with the value in the thresh_inact register . the scale factor is 31.2 m g /lsb. a value of 0 m g may result in undesirable behavior if the inactivity interrupt is enabled. register 0x26 time_inact (read/write) the time_inact register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the thresh_inact register for inactivity to be declared. the scale factor is 1 sec/lsb. unlike the other interrupt functions, which use unfiltered data (see the threshold section), the inactivity function uses filtered output data. at leas t one output sample must be generated for the inactivity interrupt to be triggered. this results in the function appearing unresponsive if the time_inact register is set to a value less than the time constant of the output data rate. a value of 0 results i n an interrupt when the output data is less than the value in the thresh_inact register . register 0x27 act_inact_ctl (read/write) d7 d6 d5 d4 act ac/dc act_x enable act_y enable act_z enable d3 d2 d1 d0 inact ac/dc inact_x enable inact_y enable inact _z enable act ac/dc and inact ac/dc bits a setting of 0 selects dc - coupled operation, and a setting of 1 enables ac - coupled operation. in dc - coupled operation, the current acceleration magnitude is compared directly with thresh_act and thresh_inact to d etermine whether activity or inactivity is detected. in ac - coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. new samples of acceleration are then compared to this reference v alue, and if the magnitude of the difference exceeds the thresh_act value, the device triggers an activity interrupt. similarly, in ac - coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. after the reference value is selected, the device compares the magnitude of the difference between the reference value and the current accel - eration with thresh_inact. if the difference is less than the value in thresh_ina ct for the time in time_inact, the device is considered inactive and the inactivity interrupt is triggered. act_x enable bits and inact_x enable bits a setting of 1 enables x - , y - , or z - axis participation in detecting activity or inactivity. a setting of 0 excludes the selected axis from participation. if all axes are excluded, the function is disabled. register 0x28 thresh_ff (read/write) the thresh_ff register is eight bits and holds the threshold value, in unsigned format, for free - fall detection. the ro ot - sum - square (rss) value of all axes is calculated and compared with the value in thresh_ff to determine if a free - fall event occurred. the scale factor is 31.2 m g /lsb. note that a value of 0 m g may
data sheet adxl350 rev. 0 | page 25 of 36 result in undesirable behavior if the free - fall interrup t is enabled. values between 300 m g and 600 m g (0x0a to 0x13 ) are recommended. register 0x29 time_ff (read/write) the time_ff register is eight bits and stores an unsigned time value representing the minimum time that the rss value of all axes must be less than thresh_ff to generate a free - fall interrupt. the scale factor is 5 ms/lsb. a value of 0 may result in undesirable behavior if the free - fall interrupt is enabled. values between 100 ms and 350 ms (0x14 to 0x46) are recommended. register 0x2a tap_axes (read/write) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 suppress tap_x enable tap_y enable tap_z enable suppress bit setting the suppress bit suppresses double tap detection if acceleration greater than the value in thresh_tap is present between taps. see the tap detection section for more details. tap_x enable bits a setting of 1 in the tap_x enable, tap_y enable, or tap_z enable bit enables x - , y - , or z - axis participation in tap detection. a setting of 0 excludes the sele cted axis from participation in tap detection. register 0x2b act_tap_status (read only) d7 d6 d5 d4 d3 d2 d1 d0 0 act_x source act_y source act_z source asleep tap_x source tap_y source tap_z source act_x source and tap_x source bits these bits indicate the first axis involved in a tap or activity event. a setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. when new data is available, these bits are not cleared but are overwritten by the new data. the a ct_tap_status register should be read before clearing the interrupt. disabling an axis from participation clears the corresponding source bit when the next activity or tap/double tap event occurs. asleep bit a setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. see the register 0x2d power_ctl (read/write) section for more information on autosleep mode. register 0x2c bw_rate (read/write) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 low_power rate low_power bit a setting of 0 in the low_power bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the power modes section for details). rate bits these bits select the device bandwidth and output data rate (see table 7 and table 8 for details). the default value is 0x0a, which translates to a 100 hz output data rate. an output data rate should be selected that is appropriate for the communication protocol and frequency selected. selecting too high of an output data rate with a low communication speed results in samples being dis carded. register 0x2d power_ctl (read/write) d7 d6 d5 d4 d3 d2 d1 d0 0 0 link auto_sleep measure sleep wakeup link bit a setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. after activity is detected, inactivity detection begins, preventing the detection of activity. this bit serially links the activity and inactivity functions. when this bit is set to 0, the inactivity and activity functions are conc urrent. additional information can be found in the link mode section. when clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was clea red. auto_sleep bit if the link bit is set, a setting of 1 in the auto_sleep bit sets the adxl350 to switch to sleep mode when inactivity is detected (that is, when acceleration has been below the thresh_inact value for at least the time indicated by time_inact). a setting of 0 disables automatic switching to sleep mode. see the description of the sleep bit in this section for more information. when clearing the auto_sleep bit, it is recommended that the part b e placed into standby mode and then set back to measure - ment mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the auto_sleep bit is cl eared may have additional noise, especially if the device was asleep when the bit was cleared. measure bit a setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. the adxl350 powers up in standby mode with minimum power consumption. sleep bit a setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. sleep mode suppre sses data_ready, stops transmission of data
adxl350 data sheet rev. 0 | page 26 of 36 to fifo, and switches the sampling rate to one specified by the wakeup bits. in sleep mode, only the activity function can be used. when clearing the sleep bit, it is recommended that the part be placed into stan dby mode and then set back to measurement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additiona l noise, especially if the device was asleep when the bit was cleared. wa k eu p bits the s e bit s c ontrol the frequency of readings in sleep mode as described in table 18. table 18 . frequency of readings in sleep mode setting d1 d0 frequency (hz) 0 0 8 0 1 4 1 0 2 1 1 1 register 0x2e int_enable (read/write) d7 d6 d5 d4 data_ready single_tap double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun setting bits in this re gister to a value of 1 enables their respective functions to generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. the data_ready, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. it is recommended that interrupts be configured before enabling their outputs. register 0x2f int_map (read/write) d7 d6 d5 d4 data_ready single_tap double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun any bits set to 0 in t his register send their respective interrupts to the int1 pin, whereas bits set to 1 send their respective interrupts to the int2 pin. all selected interrupts for a given pin are ored. register 0x30 int_source (read only) d7 d6 d5 d4 data_ready single_ta p double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun bits set to 1 in this register indicate that their respective functions have triggered an event, whereas a value of 0 indicates that the corresponding event has not occurred. the data_ready, watermark, and overrun bits are always set if the corresponding events occur, regardless of the int_enable register settings , and are cleared by reading data from the datax, datay, and dataz registers. the data_ready and watermark bits may req uire multiple reads, as indicated in the fifo mode descriptions in the fifo section. other bits, and the corresponding interrupts, are cleared by reading the int_source register. register 0x31 data_format (read/wri te) d7 d6 d5 d4 d3 d2 d1 d0 self_test spi int_invert 0 full_res justify range the data_format register controls the presentation of data to register 0x32 through register 0x37. all data, except that for the 8 g range, is clipped internally to avoid rol lover. self_test bit a setting of 1 in the self_test bit applies a self - test force to the sensor, causing a shift in the output data. a value of 0 disables the self - test force. spi bit a value of 1 in the spi bit sets the device to 3 - wire spi mode , and a value of 0 sets the device to 4 - wire spi mode . int_invert bit a value of 0 in the int_invert bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low. full_res bit when this bit is set to a value of 1, the device is in fu ll resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 2 m g /lsb scale factor. when the full_res bit is set to 0, the device is in 10 - bit mode, and the range bits determine the maximum g range and scal e factor. justify bit a setting of 1 in the j ustify bit selects left (msb) justified mode, and a setting of 0 selects right justified mode with sign extension. range bits these bits set the g range as described in table 19. table 19. g range setting setting d1 d0 g range 0 0 1 g 0 1 2 g 1 0 4 g 1 1 8 g
data sheet adxl350 rev. 0 | page 27 of 36 register 0x32 to register 0x37 datax0, datax1, datay0, datay1, dataz0, dataz1 (read only) these six bytes (register 0x32 to regis ter 0x37) are eight bits each and hold the output data for each axis. register 0x32 and register 0x33 hold the output data for the x - axis, register 0x34 and register 0x35 hold the output data for the y - axis, and register 0x36 and register 0x37 hold the out put data for the z - axis. the output data is twos complement, with datax0 as the least significant byte and datax1 as the most significant byte, where x represent x, y, or z. the data_format register (address 0x31) controls the format of the data. it is rec ommended that a multiple - byte read of all registers be performed to prevent a change in data between reads of sequential registers. register 0x38 fifo_ctl (read/write) d7 d6 d5 d4 d3 d2 d1 d0 fifo_mode trigger samples fifo_mode bits t hese bits set the f ifo mode, as described in table 20. table 20 . fifo modes setting d7 d6 mode function 0 0 bypass fifo is bypassed. 0 1 fifo fifo collects up to 32 values and then stops collecting data, collecting new data only when fifo is not full. 1 0 stream fifo holds the last 32 data values. when fifo is full, the oldest data is overwritten with newer data. 1 1 trigger when triggered by the trigger bit, fifo holds the last data samples before the trigger event and then continues to collect data until full. new data is collected only when fifo is not full. trigger bit a value of 0 in the trigger bit links the trigger event of trigger mode to int1, and a value of 1 links the trigger event to int2. samples bits the function of these bits depends on the fifo mode selected (see table 21 ). entering a value of 0 in the samples bits immediately sets the watermark status bit in the int_source register , regardless o f which fifo mode is selected. undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. table 21 . samples bits functions fifo mode samples bits function bypass none. fifo specifies ho w many fifo entries are needed to trigger a watermark interrupt. stream specifies how many fifo entries are needed to trigger a watermark interrupt. trigger specifies how many fifo samples are retained in the fifo buffer before a trigger event. 0x39 fi fo_status (read only) d7 d6 d5 d4 d3 d2 d1 d0 fifo_trig 0 entries fifo_trig bit a 1 in the fifo_trig bit corresponds to a trigger event occurring, and a 0 means that a fifo trigger event has not occurred. entries bits these bits report how many data val ues are stored in fifo. access to collect the data from fifo is provided through the datax, datay, and dataz registers. fifo reads must be done in burst or multiple - byte mode because each fifo level is cleared a fter any read ( single - or multiple - byte ) of f ifo. fifo stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device.
adxl350 data sheet rev. 0 | page 28 of 36 applications informa tion power supply decoupl ing a 1 f tantalu m capacitor (c s ) at v s and a 0.1 f ceramic capacitor (c io ) at v dd i/o placed close to the adxl350 supply pins is used for testing and is recommended to adequately decouple the accelerometer from noise on the power supply. if additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 ?, in series with v s may be helpful. additionally, increasing the bypass capacitance on v s to a 10 f tantalum capacitor in parallel with a 0.1 f ceramic c apacitor may also improve noise. care should be taken to ensure that the connection from the adxl350 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through v s . it is recommended that v s and v dd i/o be separate supplies to minimize digital clocking noise on the v s supply. if this is not possible, additional filtering of the supplies as previously mentioned may be necessary. adxl350 gnd int1 int2 cs scl/sclk sdo/alt address sda/sdi/sdio 3- or 4-wire spi or i 2 c interface v s v s c s v dd i/o v dd i/o c io interrupt control 10271-016 figure 58 . application diagram mechanical considera tions for mounting the adxl350 should be mounted on the pcb in a location close to a hard mounting point of the pcb to the case. m ounting the adxl350 at an unsupported pcb location, as shown in figure 59 , may result in large, apparent measurement errors due to undampened pcb vibration. locating t he accelerometer near a hard mounting point ensures that any pcb vibration at the accelerometer is above the accelerometers mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. mounting points pcb accelerometers 10271-010 figure 59 . incorrectly placed accelerometers tap detection the tap interrupt function is capable of detecting either single or double taps. the following parameters are shown in figure 60 for a valid single and valid doub le tap event: ? the tap detection threshold is defined by the thresh_tap register (address 0x1 d ). ? the maximum tap duration time is defined by the dur register (address 0x21). ? the tap latency time is defined by the latent register (address 0x22) and is the w aiting period from the end of the first tap until the start of the time window, when a second tap can be detected, which is determined by the value in the window register (address 0x2 3 ). ? the interval after the latency time (set by the latent register) is d efined by the window register. although a second tap must begin after the latency time has expired, it need not finish before the end of the time defined by the window register . first tap time limit for taps (dur) latency time (latent) time window for second tap (window) second tap single tap interrupt double tap interrupt threshold (thresh_tap) x hi bw interrupts 10271-0 1 1 figure 60 . tap interrupt function with valid single and double taps if only the single tap function is in use, the single tap interrupt is trigger ed when the acceleration goes below the threshold, as long as dur has not been exceeded. if both single and double tap functions are in use, the single tap inter rupt is triggered when the double tap event has been either validated or invalidated. several events can occur to invalidate the second tap of a double tap event. first, if the suppress bit in the tap_axes register (address 0x2a) is set, any acceleration s pike above the threshold during the latency time (set by the latent register) invalidates the double tap detection, as shown in figure 61. invalidates double tap if supress bit set time window for second tap (window) latency time (latent) time limit for taps (dur) x hi bw 10271-012 figure 61 . double tap event invalid due to high g event when the suppress bit is set
data sheet adxl350 rev. 0 | page 29 of 36 a double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap (set by the window register). this results in an invalid double tap at the start of this window, as shown in figure 62. additionally, a double tap event can be invalidated if an accel - eration exceeds the time limit for taps (set by the dur register), resulting in an invalid double tap at the end of the dur time limit for the second tap event, also shown in f igure 62 . invalidates double tap at start of window time window for second tap (window) latency time (latent) invalidates double tap at end of dur time limit for taps (dur) time limit for taps (dur) time limit for taps (dur) x hi bw x hi bw 10271-013 figure 62 . tap interrupt function with invalid double taps single taps, double taps, or both can be dete cted by setting the respective bits in the int_enable register (address 0x2e). control over participation of each of the three axes in single tap/ double tap detection is exerted by setting the appropriate bits in the tap_axes register (address 0x2a). for the double tap function to operate, both the latent and window registers must be set to a nonzero value. every mechanical system has somewhat different single tap/double tap responses based on the mechanical characteristics of the system. therefore, some experimentation with values for the latent, window, and thresh_tap registers is required. in general, a good starting point is to set the latent register to a value greater than 0x10, to set the window register to a value greater than 0x10, and to set the thresh_tap register to be greater than 3 g . setting a very low value in the latent, window, or thresh_tap register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs. after a tap interrupt has been received, the first axis to exceed the thresh_tap level is reported in the act_tap_status register (address 0x2b) . this register is never cleared, but is overwritten with new data. threshold the lower output data rates are achieved by decimating a common sampling frequency inside the device. the activity, free - fall, and single tap/double tap detection functions are performed using unfiltered data. since the output data is filtered, the high frequency and high g data that is used to determine activity, free - fall, a nd single tap/double tap events may not be present if the output of the accelerometer is examined. this may result in trigger events being detected when acceleration does not appear to trigger an event because the unfiltered data may have exceeded a thresh old or remained below a threshold for a certain period of time while the filtered output data has not exceeded such a threshold. link mode the function of the link bit is to reduce the number of activity interrupts that the processor must service by settin g the device to look for activity only after inactivity. for proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the int_source register (address 0x30) and, therefore, clearing the interru pts. if an activity interrupt is not cleared, the part cannot go into autosleep mode. the asleep bit in the act_tap_status register (address 0x2b) indicates if the part is asleep. sleep mode vs. low p ower mode in applications where a low data rate is suffi cient and low power consumption is desired, it is recommended that the low power mode be used in conjunction with the fifo. the sleep mode, while offering a low data rate and low average current consumption, suppresses the data_ready interrupt, preventing the accelero - meter from sending an interrupt signal to the host processor when data is ready to be collected. in this application, setting the part into low power mod e ( by setting the low_po wer bit in the bw_rate register) and enabling the fifo in fifo mod e to collect a large value of samples reduces the power consumption of the adxl350 and allows the host processor to go to sleep while the fifo is filling up. offset calibration accelerometers are mechanical st ructures containing elements that are free to move. these moving parts can be very sensitive to mechanical stresses, much more so than solid - state electronics. the 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration. additional stresses can be applied during assembly of a system containing an accelerometer. these stresses can come from, but are not limited to, component soldering, board stress during mounting, and application of any compounds on or over the component. if calibration is deemed necessary, it is recommended that calibration be performed after system assembly to compensate for these effects. a simple method of calibration is to measure the offset while assuming that the sensitivity o f the adxl350 is as specified in table 1 . the offset can then be automatically accounted for by
adxl350 data sheet rev. 0 | page 30 of 36 using the built - in offset registers. this results in the data acquired from the data r egisters already compensating for any offset. in a no - turn or single - point calibration scheme, the part is oriented such that one axis, typically the z - axis, is in the 1 g field of gravity and the remaining axes, typically the x - axis and y - axis, are in a 0 g field. the output is then measured by taking the average of a series of samples. the number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 hz or greater. this corr esponds to 10 samples at the 100 hz data rate. for data rates less than 100 hz, it is recommended that at least 10 samples be averaged together. these values are stored as x 0 g , y 0 g , and z +1 g for the 0 g measurements on the x - axis and y - axis and the 1 g mea sure - ment on the z - axis, respectively. the values measured for x 0 g and y 0 g correspond to the x - and y - axis offset, and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration. x actual = x meas ? x 0 g y actual = y meas ? y 0 g because the z - axis measurement was done in a +1 g field, a no - turn or single - point calibration scheme assumes an ideal sensitivity, s z for the z - axis. this is subtracted from z +1 g to attain the z - axis offset, which is then subt racted from future measured values to obtain the actual value: z 0 g = z +1 g ? s z z actual = z meas ? z 0 g the adxl350 can automatically compensate the output for offset by using the offset registers (register 0x1e, register 0x1f, and register 0x20). these registers contain an 8 - bit, twos complement value that is automatically added to all measured acceleration values, and the result is then placed into the data registers. because the value placed in an offset regist er is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset. the register has a scale factor of 7.8 m g /lsb and is independent of the selected g - range. as an example, assume that the adxl350 is placed into full - resolution mode with a sensitivity of typically 512 lsb/ g . the part is oriented such that the z - axis is in the field of gravity and x - , y - , and z - axis outputs are measured as +10 lsb, ?1 3 lsb, and +9 lsb, respectively. using the previous equations, x 0 g is +10 lsb, y 0 g is ?13 lsb, and z 0 g is +9 lsb. each lsb of output in full - resolution is 1.95 m g or one - quarter of an lsb of the offset register. because the offset register is additive, the 0 g values are negated and rounded to the nearest lsb of the offset register: x offset = ? round (10/4) = ?3 lsb y offset = ? round (?13/4) = 3 lsb z offset = ? round (9/4) = ?2 lsb these values are programmed into the ofsx, ofsy, and ofxz registers, respectively, as 0xfd, 0x03 , and 0xfe. as with all registers in the adxl350 , the offset registers do not retain the value written into them when power is removed from the part. power cycling the adxl350 returns the offset registers to their default value of 0x00. because the no - turn or single - point calibration method assumes an ideal sensitivity in the z - axis, any error in the sensitivity results in offset error. to help minimi ze this error, an additional measure - ment point can be used with the z - axis in a 0 g field and the 0 g measurement can be used in the z actual equation. using self - test the self - test change is defined as the difference between the acceleration output of an axis with self - test enabled and the acceleration output of the same axis with self - test disabled (see endnote 4 of table 1 ). this definition assumes that the sensor does not move betwe en these two measurements, bec ause if the sensor moves, a non - self - test related shift corrupts the test. proper configuration of the adxl350 is also necessary for an accurate self - test measurement. the part sh ould be set with a data rate that is greater than or equal to 100 hz. this is done by ensuring that a value greater than or equal to 0x0a is written into the rate bits (bit d3 through bit d0) in the bw_rate register ( address 0x2c). it is also recommended that the part be set to 8 g mode to ensure that there is sufficient dynamic range for the entire self - test shift. this is done by setting bit d3 of the data_format register ( address 0x31) and writing a value of 0x03 to the range bits (bit d1 and bit d0) o f the data_format register ( address 0x31). this results in a high dynamic range for measurement and a 2 m g /lsb scale factor. after the part is configured for accurate self - test measurement, several samples of x - , y - , and z - axis acceleration data should be retrieved from the sensor and averaged together. the number of samples averaged is a choice of the system designer, but a recom - mended starting point is 0.1 sec worth of data, which corresponds to 10 samples at 100 hz data rate. the averaged values should be stored and labeled appropriately as the self - test disabled data, that is, x st_off , y st_off , and z st_off . next, self - test should be enabled by setting bit d7 of the data_format register ( address 0x31). the output needs some time (about four samples) to s ettle after enabling self - test. after allowing the output to settle, several samples of the x - , y - , and z - axis acceleration data should be taken again and averaged. it is recommended that the same number of samples be taken for this average as was previous ly taken. these averaged values should again be stored and labeled appropriately as the value with self - test enabled, that is, x st_on , y st_on , and z st_on . self - test can then be disabled by clearing bit d7 of the data_format register ( address 0x31).
data sheet adxl350 rev. 0 | page 31 of 36 with t he stored values for self - test enabled and disabled, the self - test change is as follows: x st = x st_on ? x st_off y st = y st_on ? y st_off z st = z st_on ? z st_off because the measured output for each axis is expressed in lsbs, x st , y st , and z st are also express ed in lsbs. these values can be converted to g s of acceleration by multiplying each value by the 2 m g /lsb scale factor, if configured for full - resolution, 8 g mode. additionally, table 13 through table 16 corre spond to the self - test range converted to lsbs and can be compared with the measured self - test change. if the part was placed into full - resolution, 8 g mode, the values listed in table 13 sh ould be used. although the fixed 10 - bit mode or a range other than 8 g can be used, a different set of values, as indicated in table 14 through table 16 , would need to be used. using a ran ge below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self - test. in addition, note that the range in table 1 and the values in table 13 through table 16 take into account all possible supply voltages, v s , and no additional conversion due to v s is necessary. if the self - test change is within the valid range, the test is cons idered successful. generally, a part is considered to pass if the minimum magnitude of change is achieved. however, a part that changes by more than the maximum magnitude is not necessarily a failure.
adxl350 data sheet rev. 0 | page 32 of 36 axes of acceleration sensitivity a z a y a x 10271-021 figure 63 . axes of acceleration sensitivity (corresponding output voltage increases when accelerated along the sensitive axis) gr a vit y x out = 0 g y out = 1 g z out = 0 g x out = 0 g y out = ?1 g z out = 0 g x out = ?1 g y out = 0 g z out = 0 g x out = 1 g y out = 0 g z out = 0 g x out = 0 g y out = 0 g z out = 1 g x out = 0 g y out = 0 g z out = ?1 g 10271-022 figure 64 . output response vs. orientation to gravity
data sheet adxl350 rev. 0 | page 33 of 36 layout and design re commendations figure 65 shows the recommended printed wiring board land pattern . figure 66 and table 22 provide details about the recommended sold ering profile. 3.53mm 0.3mm 0.8mm 0.5mm 3.35mm 10271-044 figure 65 . recommended printed wiring board land pattern (dimensions shown in millimeters) t p t l t 25c to peak t s preheat critical zone t l to t p temperature time ramp-down ramp-up t smin t smax t p t l 10271-015 figure 66 . recommended soldering profile table 22 . recommended solderi ng profile 1, 2 condition profile feature sn63/pb37 pb - free average ramp rate from liquid temperature (t l ) to peak temperature (t p ) 3c/sec max 3c/sec max preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time from t smin to t smax (t s ) 60 sec to 120 sec 60 sec to 180 sec t smax to t l ramp - up rate 3c/sec max 3c/sec max liquid temperature (t l ) 183c 217c time maintained above t l (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240 + 0/?5c 260 + 0/?5c time of actual t p ? 5c (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp - down rate 6c/sec max 6c/sec max time 25c to peak temperature 6 minutes max 8 minutes max 1 based on jedec standard j - std - 020d.1. 2 for best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder pa ste used.
adxl350 data sheet rev. 0 | page 34 of 36 outline dimensions 07-13-2012-b 4.10 4.00 3.90 3.10 3.00 2.90 1.30 1.20 1.10 bot t om view top view side view 0.50 bsc 0.25 ref 0.24 ref 2.40 ref 3.40 ref 0.25 0.35 (pins 6-8, 14-16) 0.10 dia. (vent hole) 0.62 0.25 (pins 1-5, 9-13) 9 13 5 6 8 16 14 1 0.50 bsc 0.86 bsc 0.50 ref 0.13 0.64 ref 0.25 ref 0.22 bsc r 0.60 ref r 0.18 ref r 0.10 ref reference corner figure 67 . 16 - terminal chip array, small outline, no le ad cavity [lga _cav ] 4.00 mm 3.00 mm 1.2 mm body (ce - 16 - 3) dimensions shown in millimeters ordering guide model 1 measurement range ( g ) specified voltage (v) temperature range package description package option adxl350bc e z -rl 1, 2, 4, 8 2.5 ? 40c to +85c 16- terminal [lga _cav ] ce -16-3 adxl350bc e z - rl7 1, 2, 4, 8 2.5 ? 40c to +85c 16- terminal [lga _cav ] ce -16-3 eval - adxl350z evaluation board eval - adxl350z - m analog devices inertial sensor evaluation system, includes adxl350 satelli te eval - adxl350z -s adxl350 satellite, standalone 1 z = rohs compliant part.
data sheet adxl350 rev. 0 | page 35 of 36 notes
adxl350 data sheet rev. 0 | page 36 of 36 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respec tive owners. d10271 - 0 - 9/12(0)

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